1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to the monitoring and adjusting of circuit performance over the life of an electronic circuit.
2. Description of the Related Art
Over the past several decades, scaling of integrated circuits (IC's) has kept pace with Moore's Law, which states that the number of transistors on an IC doubles approximately every two years. As the number of transistors on an IC has increased, the size of the transistors has shrunk accordingly. While such integration has provided significant gains in performance per unit cost, other problems associated with higher levels of integration have occurred.
As the size of transistor features in IC's has decreased, non-idealities have begun to lessen the amount of control over individual devices. Furthermore, the reduced size has made transistors more susceptible to degradation mechanisms. Two common degradation mechanisms are hot carrier effects and negative bias temperature instability (NBTI, for PMOS devices; positive bias temperature instability, or PBTI, exists for NMOS transistors).
Hot carrier affects occur when “carriers” (either holes or electrons) gain a very high amount of kinetic energy after being accelerated by a strong electric field in areas of high field intensities in a MOS device. As a result of this high kinetic energy, hot carriers are injected and trapped in certain areas of the device, thereby forming a space charge that eventually degrades device operation and causes instability.
For NBTI, a positive charge accumulates in the channel interface of a PMOS transistor during high temperature conditions under a negative bias. This in turn results in an increase in the threshold voltage magnitude and a decrease, over time, of the drain saturation current. These effects eventually result in device instability and performance degradation of the PMOS device. PBTI is similar to NBTI, but occurs on an NMOS transistor under positive bias conditions.
At the features sizes of transistors in current IC technology, these degradation mechanisms cannot be ignored. Over time, these degradation mechanisms may impact IC performance by increasing power dissipation, reducing operating speed and/or voltage margin, irregular timing changes, and eventual failure.